Mentor Graphics :: essays papers

wise man artistic creationObjective To do it all aspects of the exercise regarding D fibre change, TTL and CMOS and to acquaint us with the HDL software package which is Mentor Graphics. This software is suitable of constructing and simulating a particular design. As for this assignment 1, we are given 4 weeks to complete the assignment. It is compulsory to attend every lab sessions as on that point is no alternative software to use. Only a certain bounce of while is given for the use of the software and in that locationfore designing of set is need to be completed before attending the lab. To give students a first-hand taking into custody of the EDA lab and most importantly Mentor Graphics, a ruling legal instrument in HDL technology.This assignment allows the students to understand or kind of inform themselves with the design flow of the EDA software and to fully explore what the software is undefended and powerful to do.Lastly, to prepare the students f or the next assignments which uses the similar software. Introduction D(elay) exchange (What You defy to Know First) The D tack together is useful when a single data bit (1 or 0) is to be stored. An additional inverter to the S-R flip-flop at the R input creates a D flip-flop. The D flip-flop shown on a lower floor is a modification of the timeed SR flip-flop. The D input goes outright into the S input and the complement of the D input goes to the R input. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The rectitude table below summarizes the operations of the positive spring-triggered D flip-flop. As before, the ban edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.(a) Logic diagram with NAND gates (b) Graphical attribute InputsD CP(CLK) OutputsQ QComments1 1 0SET (stores 1)Mentor Graphics essays papersMentor GraphicsObjective To complete all aspects of the exercise regarding D type flip-flop, TTL and CMOS and to familiarize us with the HDL software which is Mentor Graphics. This software is capable of constructing and simulating a particular design. As for this assignment 1, we are given 4 weeks to complete the assignment. It is compulsory to attend every lab sessions as there is no alternative software to use. Only a certain limit of time is given for the use of the software and therefore designing of circuit is required to be completed before attending the lab. To give students a first-hand understanding of the EDA lab and most importantly Mentor Graphics, a powerful tool in HDL technology.This assignment allows the students to understand or rather familiarize themselves with the design flow of the EDA software and to fully explore what the software is capable and powerful to do.Lastly, to prepare the students for the next assignments which uses the similar software. Introduction D(elay) Flip-Flop (What You Have to Know First) The D flip-flop is useful when a single data bit (1 or 0) is to be stored. An additional inverter to the S-R flip-flop at the R input creates a D flip-flop. The D flip-flop shown below is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarizes the operations of the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.(a) Logic diagram with NAND gates (b) Graphical symbol InputsD CP(CLK)OutputsQ QComments1 1 0SET (stores 1)